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Posted in Research Topics.

GRIP Parallel Processing Architecture

How can system architecture be best designed as an efficient target for a PFP compiler? GRIP (Graph Reduction In Parallel) explored the design space using stock processors and custom hardware such as intelligent memory units, and new compilation and run-time system technology were successfully demonstrated.

Elements of GRIP were eventually transferred to industry and incorporated into the ICL "Goldrush" parallel database server.

The GRIP architecture and its programing paradigm for PFP are described in the following papers:

  • GRIP: the GRIP Multiprocessor (Clack, in Parallel Computing Principles and Practice, ed. T. J. Fountain, Chapter 7, pp 266-275, ISBN 0-521-45131-0, CUP 1990).
  • High Performance Parallel Graph Reduction (Peyton Jones, Clack and Salkild), LNCS 365:193-206, ISSN 0302-9743, Springer 1989). This paper is also reprinted as:
    • High Performance Parallel Graph Reduction (Peyton Jones, Clack and Salkild, in Programming Languages for Parallel Processing, eds. D. Skillicorn and D.Talia, Chapter 5, pp 234-247, ISBN 0-8186-6502-5, IEEE Computer Society Press 1994). Described as a collection of reprints of "the most important parallel-programming languages designed in the last decade".
  • Functional Programming on the GRIP multiprocessor (Peyton Jones, Clack, Salkild and Hardie, in Proceedings IEE International Specialist Seminar on Design and Application of Parallel Digital Processors, pp 116-127, available electronically from the IEEE at this link, IEEE. 1988)
  • GRIP - a parallel graph reduction machine (Peyton Jones, Clack, and Salkild), ICL Technical Journal 5(3):595-599, ISSN 0142-1557, OUP 1987).
  • GRIP - a high performance architecture for parallel graph reduction (Peyton Jones, Clack, Salkild and Hardie, LNCS 274:98-112, ISSN 0302-9743, Springer 1987). This paper is also reprinted (plus an additional two pages) as:
    • GRIP - a high performance architecture for parallel graph reduction (Peyton Jones, Clack, Salkild and Hardie, in Multiprocessor Computer Architecture, eds. T. J. Fountain and M. J. Shute, Chapter 5, pp 101-120, ISBN 0-444-88215-4, Elsevier 1990)